The field of the invention generally relates to high speed clock recovery systems, and more particularly relates to an integrated CMOS circuit that provides a precise 90.degree. phase delay or shift at a desired frequency.
As is well known, high speed data is usually transmitted and received in a non-return-to-zero (NRZ) format to minimize distortion by reducing the high frequency content of the signals. For example, consider a string of incoming data 10010 in a NRZ format at a 200 Mbit/sec rate where each bit uses a full period of 5 nanoseconds. The receiver has to generate a clock, usually referred to as the "recovered clock", at exactly 200 MHz, and align the clock with respect to the incoming data. For example, it is desirable that the positive transitions of the recovered clock occur at the exact middles of the data bits where one would expect the maximum voltage if the received bit is a logical "1", or the minimum voltage if the received bit is a logical "0". Once the clock is recovered, the NRZ signals and the recovered clock are respectively fed to the "data" and "clock" inputs of a flip-flop which functions as a decision device. That is, the flip-flop will be clocked by the recovered clock, and the output will be the recovered data in a clean "1" or "0" state.
Since the desired clock frequency does not appear in the frequency spectrum of the NRZ data, a non-linear operation is normally applied to the incoming data to generate a frequency component containing the clock frequency. In a typical prior art approach, the incoming NRZ data is delayed by 90.degree. in a phase shifter, and the original and delayed NRZ data are fed to an exclusive 0R (XOR) gate. As is well known, the output of the XOR will have a frequency component corresponding to the originating or desired clock. The output of the XOR is then fed to a phase comparator or detector along with the output of a voltage controlled oscillator (VCO) or current controlled oscillator (CCO). The phase comparator and the VCO or CCO are part of a phase-locked loop. That is, the output of the phase comparator is used to generate a control voltage or current to the VCO or CCO such that the VCO or CCO is finally brought to oscillate at the same frequency as the originating clock of the incoming NRZ data. However, the VCO or CCO output can not be used to clock the decision device or flip-flop because it is not aligned at the optimum decision point at the middle of the bit period. Thus, it is necessary to provide a clock that is 90.degree. out-of-phase or is in quadrature with the VCO or CCO output. This quadrature clock is then used to clock the decision device, and it catches the NRZ data at the optimum decision points at the exact middles of data bits. Typically, the quadrature clock is generated by running the VCO or CCO at twice the needed frequency and using divide-by-2 circuits. One drawback of running the VCO or CCO at twice the needed frequency is that more advanced and expensive technologies are generally required.
Referring back to the incoming NRZ data before the exclusive OR, a precise 90.degree. phase shift is required. Otherwise, the recovered clock will not be aligned with the positive clock transitions occurring exactly at the middle of the data bits, and errors in recovered data may occur. One possible prior art approach is described in H. Ransijn and P. O'Connor, "A PPL-based 2.5 Gb/s GaAs Clock and Data Generator IC", IEEE Journal of Solid-State Circuits, Vol 26, October 1991, pp 1345-1353. An input is fed to a branch wherein one leg has a series resistor followed by a capacitor to ground, and the other leg has a series capacitor followed by a resistor to ground. With such arrangement, two outputs are produced, and one always lags the other by 90.degree.. Thus, a 90.degree. phase shift can be provided for the incoming NRZ data. One problem with this arrangement is that the amplitudes of the two outputs are different. Thus, additional phase delays will be introduced into following circuits except at one frequency w.sub.o where EQU w.sub.o =1/[RC]
In an integrated circuit, it is difficult to control the absolute values of resistors R and capacitors C. Typically, the resistance of integrated resistors may vary by plus or minus 30% for wafers processed in different lots, and the capacitance C may typically vary by plus or minus 15%. Therefore, it is very difficult to provide equal amplitudes unless costly trimming is added.